The AT91SAM7L128 is a member of a series of high-performance, ultra-low power ARM7TDMI-based Processor. The ARM7TDMI RISC processor based on ARMv4T Von Neumann Architecture, runs at up to 36 MHz, providing 0.9 MIPS/MHz. Two instruction sets: ARM high-performance 32-bit instruction set and Thumb high code density 16-bit instruction set. Three-stage pipeline architecture: 1. Instruction Fetch (F), 2. Instruction Decode (D) and 3. Execute (E).
- 128 Kbytes of Flash Memory (AT91SAM7L128) - Single plane, One bank of 512 pages of 256 bytes, 10,000 write cycles, 10-year data retention capability, Protection Mode to secure contents of the Flash.
- 64 Kbytes of Flash Memory (AT91SAM7L64) - Single plane, One bank of 256 pages of 256 bytes.
- 6 Kbytes of Fast SRAM - Single-cycle access at full speed, 2 Kbytes of Backup SRAM, 4 Kbytes of Core SRAM.
- Programmable Bus Arbiter - Handles requests from the ARM7TDMI and the Peripheral DMA Controller.
- Address decoder provides selection signals for Five internal 1 Mbyte memory areas and One 256 Mbyte embedded peripheral area.
- Abort Status Registers which has a Source, Type and all parameters of the access leading to an abort are saved and Facilitates debug by detection of bad pointers.
- Misalignment Detector.
- Remap Command that remaps the SRAM in place of the embedded non-volatile memory. Allows handling of dynamic exception vectors. Peripheral protection against write and/or user access.
- Enhanced Embedded Flash Controller.